1. Field of the Invention
The invention relates to a method for adjusting signal propagation time in a memory system in which a controller is connected to at least one memory chip via a plurality of connecting lines. The subject matter of the invention also relates to circuit arrangements for performing this method. A preferred, but not exclusive, field of application is memory systems with RAM (Random Access Memory) chips, particularly with synchronous dynamic RAMs (SDRAMS). The subject matter of the invention also relates to circuit arrangements in controllers of memory chips for performing the adjustment method.
2. Description of the Related Art
The communication between one or more memory chips and a common controller in a memory system takes place under clock control. Both the memory data and the control signals, which are to be transmitted, are transferred to the connecting lines at the respective transmission end as bits (binary samples). At the respective reception end, the data and control signals received via the connecting lines are sampled using suitably positioned clock edges. These clock edges must each come in the validity time of the bits, i.e. they must each appear within that period of time in which the level of the signal to be sampled explicitly represents the logic value of the transmitted bit.
In order to synchronize the signal transmission, it is necessary to transmit, together with the data and control signals, at least one time reference signal from which it is possible to derive the clock edges for correct-time sampling of the received bits at the reception end. Normally, each memory chip has two separate transmission lines for time reference signals connected to it, a clock signal line for transmitting a clock signal from the controller to the memory chip and a strobe signal line for transmitting a data strobe signal between the controller and the memory chip. The clock signal is used in the memory chip as a time reference for the storage operations and is also used as a time reference for sampling the control signals, which include both binary-coded instruction signals for initiating the various storage operations and the binary-coded address signals for selectively addressing the memory cells within the memory chip. The data strobe signal is generated in the write mode in the controller and, together with the write data, is transmitted to the memory chip and forms the time reference for sampling the write data. In the read mode, the data strobe signal is generated in the memory chip and, together with the read data, is transmitted to the controller and forms the time reference for sampling the read data.
It is an object of the system designer to ensure that the phase relationships between the various signals are respectively kept within firmly prescribed tolerance limits both at the transmission end and at the reception end. Observing the phase relationships at the reception end is a problem particularly when various signals are transmitted via connecting lines having different signal propagation times. Propagation time differences along the connecting lines may arise if the lines are of different lengths. For this reason, great care has been taken to date to make the connecting lines of the same length as far as possible and to minimize propagation time differences as a result.
This solution is unsatisfactory, however. First, layout problems may arise when the line lengths are given the same proportions, particularly if a controller communicates with a plurality of memory chips which are at different physical distances from the controller. Secondly, besides the geometric length, there are also other factors which affect the propagation speed of the signals along the lines and hence the propagation time, e.g. the width of the conductor tracks, their geometric relationship to the conductors of the respective reference potentials (ground or supply potential) and also their surroundings if stray fields reach said surroundings.
The aforementioned propagation time differences could be compensated for at the transmission or reception end by suitable delay devices. Generally, controllers and memory chips are produced as separate units, normally as integrated and ready-encapsulated circuits (chips), so that they can be combined arbitrarily to form a memory system of desired size and configuration. For this reason, it is almost impossible to predict all of the features of the connecting lines used in the combined memory system which determine propagation time. To set the delay devices appropriately, it would be possible to measure the phases of the signals received via various connecting lines relative to a respective reference phase, e.g. relative to the phase of the received clock signal, on the memory chip. This would require a respective phase comparator to be provided in the memory chip for each signal which is to be measured. However, it is almost impossible to measure large propagation time differences explicitly according to magnitude and arithmetic sign using pure phase comparison, particularly if these differences are more than one clock period. Problems may thus arise with progressive development, which aims at ever higher clock frequencies.
US 2003/0200407 A1 discloses a method and a circuit arrangement for adjusting propagation time differences in a memory system in which connections of a controller are connected to connections of a memory chip via a plurality of connecting lines, where in addition to the connecting lines there are dummy connecting lines between the controller and the memory chip which have a reflective termination at the memory chip end and are connected to an evaluation unit at the controller end. These dummy signal lines, whose length corresponds to that of the regular data and signal connecting lines, can then be used to form echo measurements and the ascertained propagation time differences can then be compensated for using delay devices.